1. Field of the Invention
The invention relates to magnetic RAM (MRAM), or any memory cells based on resistance difference, and more particularly for improving reliability and overall yield by using stress testing.
2. Description of the Related Art
Stress testing of MRAMs (magnetic or magnetoresistive RAMs) has been attracting the attention of memory system designers because of the ultrathin layer of the insulator of about 1 nm (1 nanometer or 10 Angstrom). Control of the thickness is critical but the thickness will vary in the manufacturing process. Memory systems designers have come up with various methods of testing to weed out magnetic tunnel junctions which do not meet the required minimum thickness and which will lead eventually to failures. A common technique is voltage stress testing. A higher voltage than the standard voltage is applied to the MRAM which causes excess current to flow through the junction, stressing it and leading to failure. These failed cells can then be replaced with redundant cells.
U.S. patents which relate to testing of memories and MRAMs are:    U.S. Pat. No. 6,990,024 (Hidaka) discloses a MRAM with a circuit which determines the tunnel current depending on the manufacturing irregularity of the tunneling film thickness. Using current instead of voltage thus avoids excessive tunnel current. This method secures a data read margin to correspond to the manufacturing irregularity of the thickness of a tunneling film and can further provide a higher current than the normal one in a burn-in test.    U.S. Pat. No. 6,894,937 (Garni et al.) describes a circuit which provides a stress voltage to Magnetic Tunnel Junctions (MTJs) to provide a predetermined acceleration of aging compared to normal operation. The stress voltage is maintained at the desired voltage by a circuit that mocks the loading characteristics of the portion of the memory array being stressed.    U.S. Pat. No. 6,831,872 (Matsuoka.) discloses a means for determining whether the reference level stored in the reference cell is within a preset range after a number of read operations and correction means for correcting the reference level if not within a specified range. This U.S. Patent specifically addresses the testing of a Novel Resistance Control Nonvolatile RAM (RRAM), but points out that its method can also be employed for a MRAM.    U.S. Pat. No. 6,760,865 (Ledford et al.) teaches a Built-In Self-Test (BIST) controller having a sequencer which identifies the test algorithm that is to be performed. This U.S. Patent allows the testing of multiple memories which may be different regarding type, size, data widths, etc. and is geared towards Flash or Electrically Erasable arrays, but DRAM, SRAM, MRAM and FeRAM (Ferroelectric RAM) may be also used.    U.S. Pat. No. 6,347,056 (Ledford et al.) is similar to U.S. Pat. No. 6,760,865 above.
It should be noted that none of the above-cited examples of the related art address the need of stressing the cells of a MRAM with voltage and current above the normal operating conditions to weed out random failures and to replace these failed cells with redundant cells that passed the stress test. These needs are met by the invention, which provides a method and implementation to weed out said random failures and replaces these failed cells as will be apparent by the description and drawing of the present invention.